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sercon410b datasheet
use in life support devices or systems must be expressly authorized. sgs-thomson products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. as used herein : 1. life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when prop- erly used in accordance with instructions for use pro- vided with the product, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can reason- ably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
sercon410b datasheet index page number sercon410b .................................... 1 1 general description ................... ............ 5 2 pin description ........................................ 6 3 electrical characteristics ......... .. ....... ....... ...... 9 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 recommended operating . . . . . . . . . . . . . . . . . . . . . . . . ...... 9 3.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.1 clock input mclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.2 clock input sclk . . . . . . . . . ........................ 11 3.4.3 serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4.4 address latch . . . . . . . . . . . . . . . . . . . . . . . . .......... 12 3.4.5 read access of control registers . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.6 read access of dual port ram . . . . . . . . . . . . . . . .......... 14 3.4.7 write access to control registers . . . . . ................... 15 3.4.8 write access to dual port ram . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 control registers and ram data structures .................... 17 4.1 control register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 data structures within the ram . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 telegram headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.2 data containers . . . . . . . . . . . . . . . . . . . . . ............ 25 4.2.3 end marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.4 service containers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 package mechanical data ................................. 29 6 additional support and tools .............................. 29 6.1 sercos interface specification . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 software and boards for the sercon410b . . . . . . . . . . . . . . . . . . 29 ?
notes: ? sercon410b
sercon410b preliminary data ? this is preliminary data from sgs-thomson. details are subject to change without notice. may 1994 sercos interface controller (ordering number: SERGBQA) pqfp100 single-chip controller for sercos interface real time communication for industrial control systems 8/16-bit bus interface, intel and motorola con- trol signals dual port ram with 1024 words * 16-bit data communications via optical fiber rings, rs 485 rings and rs 485 busses maximum transmission rate of 4 mbaud with in- ternal clock recovery maximum transmission rate of 10 mbaud with external clock recovery internal repeater for ring connections full duplex operation modulation of power of optical transmitter diode automatic transmission of synchronous and data telegrams in the communication cycle flexible ram configuration, communication data stored in ram (single or double buffer) or transfer via dma synchronization by external signal timing control signals automatic service channel transmission 100-pin plastic flat-pack casing 1/30
figure 1. sercon410b block diagram ? sercon410b 2/30
figure 2. sercon410b pin configuration ? sercon410b 3/30
figure 3. sercos interface with ring connection figure 4. sercon410b with rs-485 bus connection ? sercon410b 4/30
1 general description the sercos interface controller sercon410b is an integrated circuit for sercos interface com- munication systems. the sercos interface is a digital interface for communication between sys- tems which have to exchange information cycli- cally at short, fixed intervals (65 m s to 65 ms). it is appropriate for the synchronous operation of dis- tributed control or test equipment (e.g. connection between drives and numeric control). a sercos interface communication system con- sists of one master and several slaves (fig. 3). these units are connected by a fiber optical ring. this ring starts and ends at the master. the slaves regenerate and repeat their received data or send their own telegrams. by this method the telegrams sent by the master are received by all slaves while the master receives data telegrams from the slaves. the optical fiber assures a reliable high- speed data transmission with excellent noise im- munity. the sercos interface controller contains all the hardware-related functions of the sercos inter- face and considerably reduces the hardware costs and the computing time requirements of the microprocessor. it is the direct link between the electro-optical receiver and transmitter and the mi- croprocessor that executes the control algorithms. the sercon410b can be used both for sercos interface masters and slaves. the circuit contains the following functions (fig. 1): - interface to the microprocessor with a data bus width of 8 or 16 bits and with control lines according to intel or motorola standards. - a serial interface for making a direct connec- tion with the optical receiver and transmitter of the fiber optic ring or with drivers to an electric ring or bus. data and clock regeneration, the repeater for ring topologies and the serial transmitter and receiver are integrated. the signals are monitored and test signals gener- ated. the serial interface operates up to 4mbaud without external circuitry and up to 10 mbaud with external clock regeneration. - a dual port ram (1024 * 16 bit) for control and communication data. the organization of the memory is flexible. - telegram processing for automatic transmis- sion and monitoring of synchronous and data telegrams. only transmission data which is in- tended for the particular interface user is proc- essed. the transmitted data is either stored in the internal ram (single or double buffer) or transferred via direct memory access (dma). the transmission of service channel informa- tion over several communication cycles is exe- cuted automatically. in addition to the sercos interface the ser- con410b can also be used for other real-time communications tasks. as an alternative to the fi- beroptical ring also bus topologies with rs-485 signals are supported (fig. 4). the sercon410b is therefore suitable for a wide range of applica- tions. ? sercon410b 5/30
2 pin description signal (s) pin (s) io function d15-0 77-80, 82-85, 87-90, 92-95 i/o data bus: for 8-bit-wide bus interfaces, data is written to and read via d7-0, for 16-bit-wide bus interfaces via d15-0. when admux is 1, the address which is stored in the address latch with alel and aleh is input via d15-0. a15-0 56-59, 61-64, 66-69, 71-74 i/o address bus: when admux is 0 the pins are inputs, when admux is 1, they are outputs for the address stored with alel (a7-0) and aleh (a15-8). in the 8-bit bus mode, a0 distinguishes which byte is transmitted via d7-0 (depends on bytedir). in the 16-bit bus mode, data is tansferred via d7-0 only when a0 is 0. a10-1 selects the words of the internal ram; a6- 1the control registers. alel, aleh 54, 53 i address latch enable, low and high, active high: they are only used when admux is 1. when alel/aleh is 1, the signals go from the data bus to the address bus, when alel/aleh = 0, they store the address. when admux is 0, alel/aleh have to be connected to v dd . rdn 51 i read: for the intel bus interface, data is read when rdn is 0. for the motorola bus interface, data is read or written to when rdn is 0 (busmode1 = 0) or rdn is 1 (busmode1 = 1). wrn 52 i write: for the intel bus interface, data is written to when wrn is 0. for the motorola bus interface, wrn selects read (wrn = 1) and write (wrn = 0) operations of the data bus. bhen 75 i byte high enable, active low: in the 16-bit bus mode, data is transferred via d15-8 when bhen is 0. mcsn0, mcsn1 46,47 i memory chip select, active low: to access the internal ram mcsn0 and mcsn1 must be 0. pcsn0, pcs1 48,49 i periphery chip select, active low (pcsn0) and active high (pcsn1): to access the control registers pcsn0 must equal 0 and pcs1 must equal 1. busyn 45 o ram busy, active low: becomes active if an access to an address of the dual port ram is performed simultaneously to an access to the same memory location by the internal telegram processing. dmareqr 38 o dma request receive, active high: becomes active if data from the receive fifo can be read. at the beginning of the read operation of the last word of the receive fifo, dmareqr becomes inactive. dmaackrn 40 i dma acknowledge receive, active low: when dmaackrn is 0, the receive fifo is read, independent of the levels on a6-1 and the chip select signals. dmareqt 39 o dma request transmit, active high: becomes active when data can be written to the transmit fifo. dmareqt becomes inactive again at the beginning of the last write access to the transmit fifo. dmareqtn 41 i dma acknowledge transmit, active low: when dmaacktn is 0, the transmit fifo is written to when there is a bus write access independent of the levels on a6-1 and the chip select signals. admux 96 i address data bus: when admux is 0 a15-0 are the address inputs, when admux is 1 a15-0 are the outputs of the address latch. busmode0, busmode1 97,98 i bus mode: busmode0 = 0 turns on the intel bus interface (rdn = read, wrn = write), busmode0 = 1 selects the motorola interface (rdn = data strobe, wrn = read/write). busmode1 selects the 0-active data strobe (busmode1 = 0) or the 1-active data strobe (busmode1 = 1). buswidth 99 i bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). table 1. sercon410b i/o port function summary ? sercon410b 6/30
pin description (continued) signal (s) pin (s) io function bytedir 100 i byte address sequence: when bytedir is 0, a0 = 0 addresses the lower 8 bits of a word (low byte first), when bytedir is 1, the upper 8 bits of a word are addressed (high byte first). int0, int1 44,43 o interrupts, active low or active high. interrupt sources and signal polarity are programmable. sregen 28 i internal regeneration. when sregen is 0, clock and data regeneration are turned off. rxc and txc are clock inputs. when sregen is 1, clock and data regeneration are turned on. rxc and txc output the internally generated clocks. sbaud 29 i baud rate. when regeneration is turned on, sbaud selects the baud rate (f sclk/ 16 when sbaud is 0, f sclk /32 when sbaud is 1). can be overwritten by the microprocessor. rxd 14 i receive data for the serial interface. rxc 12 i/o receive clock for the serial interface. when regeneration is turned off (sregen = 0), clock input for the serial receiver and transmitter (only when repeater is turned on); when regeneration is turned on (sregen = 1) output of the internally generated receive clock. the maximum frequency is 10 mhz. recactn 26 o receive active, active low. indicates that the serial receiver is receiving a telegram. txd1 16 o transmit data. the pin can be switched to a high impedance state. txd6-2 22,21,2 0, 18,17 o transmit data or output port. the pins either output the serial data or can be used as parallel output ports. when they output transmit data, each pin can be switched to a high impedance state individually. txdnrz 24 o nrz-coded transmit data. txc 13 i/o transmit clock for the serial interface. when regeneration is turned off (sregen = 0) and the repeater is turned off, it is the clock input for the serial transmitter; when regeneration is turned on (sregen = 1) it is the output for the internally generated transmit clock. the maximum frequency is 10 mhz. idle 25 o transmitter active, active low. when transmitting own data idle is 0. tm0, tm1 30,31 i turn on test generator: tm0 = 0 switches txd1-6 to continuous signal light, tm1 = 0 switch-over to zero bit stream. the processor can overwrite the level of tm1-0. l_errn 32 o line error, active low: goes low when signal distortion is too high or when the receive signal is missing. the operating mode is programmed by the processor. cyc_clk 34 i sercos interface cycle clock: cyc_clk synchronizes the communication cycles. the polarity is programmable. con_clk 35 o control clock: becomes active within a communication cycle. time, polarity and width are programmable. div_clk 36 o divided control clock: becomes active several times within a ommunication cycle. number of pulses, start time, repetition rate and polarity are programmable, the pulse width is 1 m s. sclk 2 i serial clock for clock regeneration: the frequency is 16 or 32 times the baud rate, the maximum frequency is 64 mhz. table 1. sercon410b i/o port function summary (continued) ? sercon410b 7/30
signal (s) pin (s) io function sclko2 6 o clock output: outputs the sclk clock divided by 2. sclko4 5 o clock output: outputs the sclk clock divided by 4. mclk 4 i master clock for telegram processing and timing control, frequency 12 to 20 mhz. rstn 10 i reset, active low. must be zero for at least 50 ns after power on. test 7 i test, active high. has to be tied to v ss . outz 11 i puts outputs into high impedance state, active high: outz is 1 puts all pins into a high impedance state. the clocks are turned off and the circuit is reset. for the in-circuit test and for turning on the powerdown mode. ndtro 9 o nand tree output. for the test at the semiconductor manufacturers and for the connection test after board production. ndtro is not set to a high impedance state. v ss 3,15,23, 33,42, 50,60, 70,81, 91 ground pins. v dd 1,8,19, 27,37, 55,65, 76,86 power supply +5 v 5%. table 1. sercon410b i/o port function summary (continued) pin description (continued) ? sercon410b 8/30
3 electrical characteristics 3.1 absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3 to 7.0 v v i input voltage v ss - 0.3 to v dd + 0.3 v v o output voltage v ss - 0.3 to v dd + 0.3 v t stg storage temperature -55 to +150 c 3.2 recommended operating conditions symbol parameter value unit min. max. t a operating temperature -40 85 c v dd operating supply voltage 4.75 5.25 v f sclk clock frequency sclk 64 mhz f mclk clock frequency mclk 20 mhz f txc ,f rxc clock frequency txc, rxc 10 mhz symbol parameter test conditions value unit min. typ. max. v il input low level voltage 0.8 v v ih input high level voltage 2.4 v v t+ schmitt trig. +ve threshold all pins except d15-0, a15-0, alel, aleh, rdn, wrn, bhen, mcsn0-1, pcsn0, pcs1, dmaacktn, dmaackrn 2.0 2.4 v vt- schmitt trig. +ve threshold 0.6 0.8 v (v dd =5v 5% ta = -40 c to +85 c, unless otherwise specified) 3.3 dc electrical characteristics ? sercon410b 9/30
symbol parameter test conditions value unit min. typ. max. i il low level input current (pull-up resistor) vi = v ss -450 -50 -30 m a i ih high level input current vi = v dd -10 <1 10 m a v ol low level output voltage, all o- and i/o-pins except txd6-1 i oi = -4 ma 0.4 v v oh high level output voltage, all o- and i/o-pins except txd6-1 i oh = +4 ma 2.4 v v ol high level output voltage, all o- and i/o-pins except txd6-1 i oi = -8 ma 0.4 v v oh high level output voltage, pins txd6-1 ioh = +8 ma v dd - 0.5 i oz tri-state output leakage v o =0vorv dd -10 <1 +10 m a i klu i/o latch-up current vv dd 200ma ma v esd electrostatic protection c=100 pf, r = 1.5 k 2000 v c pin pin capacitance 10 pf dc electrical characteristics (continued) ? sercon410b 10/30
figure 5. timing of clock mclk and related outputs (c load =50pf,v dd =5v 5% t a = -40 c to +85 c) 3.4 ac electrical characteristics 3.4.1 clock input mclk symbol parameter value unit min. type max. f mclk clock frequency mclk 12 20 mhz t mclk0 mclk low 20 ns t mclk1 mclk high 20 ns t mcld output delay rising edge mclk to dmareqr/t, con_clk, div_clk 30 ns figure 6. timing of clock sclk 3.4.2 clock input sclk symbol parameter value unit min. type max. f sclk clock frequency sclk 64 mhz t sclk0 sclk low 6.5 ns t sclk1 sclk high 6.5 ns ? sercon410b 11/30
figure 7. timing of serial clock inputs rxc and txc and related signals ac electrical characteristics (continued) 3.4.3 serial clock symbol parameter value unit min. type max. f rtxc clock frequency rxc, txc 10 mhz t rtxc0 rxc, txc low 40 ns t rtxx1 rxc, txc high 40 ns t rtout output delay rxc, txc to txd6-1, txdnrz, idle, recactn 45 ns t rxdsu setup rxd to falling edge of rxc 15 ns (sregen = 0, external clock regeneration, rxc and txc are inputs) figure 8. timing of serial clock inputs rxc and txc and related signals 3.4.4 address latch symbol parameter value unit min. type max. t alew pulse width alel, aleh 25 ns t alesu setup time d15-0 to falling edge aleh, alel 10 ns t alehd hold time falling edge aleh, alel to d15-0 5 ns t da delay from d15-0 to a15-0 20 ns ? sercon410b 12/30
figure 9. read access of control registers ac electrical characteristics (continued) 3.4.5 read access of control registers symbol parameter value unit min. type max. t asu setup time a6-0, bhen, pcsn0, pcs1, dmaacknr, wrn (only motorola mode) to falling edge rdn (intel or motorola mode with low active strobe) or rising edge rdn (motorola mode with high active strobe) 0ns t ahd hold time a10-0, bhen, mcsn0-1, wrn (only motorola mode) to rising edge rdn (intel motorola mode with low active strobe) or falling edge rdn (motorola mode with high active strobe) 0ns t pad access time a6-0, bhen, pcsn0, pcs1, dmaacknr, wrn (only motorola mode) to d15-0 valid 50 ns t prdd access time rdn to d15-0 valid 40 ns t rdz delay rdn to d15-0 high-z 15 ns t prq delay rdn to dmareqr low 30 ns ? sercon410b 13/30
figure 10. read access of dual port ram ac electrical characteristics (continued) 3.4.6 read access of dual port ram symbol parameter value unit min. type max. t asu setup time a10-0, bhen, mcsn0-1, wrn (only motorola mode) to falling edge rdn (intel or motorola mode with low active strobe) or rising edge rdn (motorola mode with high active strobe) 0ns t ahd hold time a10-0, bhen, mcsn0-1, wrn (only motorola mode) to rising edge rdn (intel motorola mode with low active strobe) or falling edge rdn (motorola mode with high active strobe) 0ns t mrdd access time rdn to d15-0 valid 60 ns t mbsy delay rdn to busyn low 35 ns t mbhd delay busyn high to d15-0 valid 30 ns t rdz delay rdn to d15-0 high-z 15 ns t rd1 rdn and wrn high after end of read access 30 ns ? sercon410b 14/30
figure 11. write access to control registers ac electrical characteristics (continued) symbol parameter value unit min. type max. t asu setup time a6-0, bhen, pcsn0, pcs1, dmaacknt, wrn (only motorola mode) to falling edge wrn (intel mode) or rdn (motorola mode, strobe active low) or rising edge rdn (motorola mode, strobe active high) 0ns t ahd hold time a6-0, bhen, pcsn0, pcs1, dmaacknt, wrn (only motorola mode) to rising edge wrn (intel mode) or rdn (motorola mode, strobeactive low) or falling edge rdn (motorola mode, strobe active high) 0ns t pwrw pulse width wrn (intel mode) or rdn (motorola mode) 30 ns t dsu setup time d15-0 to end of write access 10 ns t dhd hold time d15-0 to end of write access 10 ns t prq delay wrn or rdn to dmareqt low 30 ns 3.4.7 write access to control registers ? sercon410b 15/30
figure 12. write access to dual port ram ac electrical characteristics (continued) symbol parameter value unit min. type max. t asu setup time a10-0, bhen, mcsn0-1, wrn (only motorola mode) to falling edge of wrn (intel mode) or rdn (motorola mode with low active strobe) or rising edge rdn (motorola mode with high active strobe) 0ns t ahd hold time a10-0, bhen, mcsn0-1, wrn (only motorola mode) to rising edge of wrn (intel mode) or rdn (motorola mode with low active strobe) or rising edge rdn (motorola mode with high active strobe) 0ns t mwrw pulse width wrn or rdn 30 ns t dsu setup time d15-0 to end of write access 10 ns t dhd hold time d15-0 after end of write access 10 ns t mbsy delay wrn or rdn (begin of write access) to busyn low 35 ns t mbhwh setup time busyn high to end of write access 30 ns t wr1 wrn and rdn high after end of write access 40 ns 3.4.8 write access to dual port ram ? sercon410b 16/30
4 control registers and ram data structures 4.1 control register addresses the following table is an overview of the control registers. the address is the word address which is input by a6-1. to calculate the byte address, the value has to be multiplied by two. the reset val- ues of the control registers are shown in bold . a6-1 bit name r/w value function 0h 0-15 version r 2 circuit code (0002h) 1h 0 rstfl r/w 0 1 reset has not taken place reset has taken place 1 swrst w 0 1 do not reset reset by software 2 (not used) 3 repon r/w 0 1 repeater turned off repeater turned on 4 sregen r level at sregen pin 5 regmode r/w 0 1 sampling at the middle of bit sampling according to sercos interface specification 6 r/w 0 1 baud rate = f sclk /16 baud rate = f sclk /32 7 polrxd r/w 0 1 alight ono when rxd = 0 alight ono when rxd = 1 8 presync r/w 0 1 no pre-frame sync word pre-frame sync word 9 poltxd r/w 0 1 alight ono when txd = 0 alight ono when txd = 1 10 entsbaud r/w 0 1 baud rate selected by swsbaud pin baud rate selected by swsbaud control bit 11 sbaud r level at pin sbaud 12 rxdnrz r/w 0 1 receive data is nrzi-coded receive data is nrzi-coded 13 wrsync r/w direct ram write access ram write access internally synchronized 14 dmamode r/w 0 1 dmareqr/dmareqt are static signals dmareqr/dmareqt are pulses 15 (not used) all control registers can be written to and read (r/w), with the exception of the control bits that initiate an action (w). the status registers can only be read (r). when control registers which contain bits that are not used or can only be read, are written to, these bits can be set to 0 or 1; they are not evaluated internally. if control registers are read with bits that are not used, these bits are set to 0. ? sercon410b 17/30
control register addresses (continued) a6-1 bit name r/w value function 2h 0-5 entxd1-6 r/w 0 1 pin txdn has a high impedance pin txdn is outputting transmit data 6 txdmode r/w 0 1 txdmode txd2-6 is outputting entxd2-6 7-9 tmode0-2 r/w 0-3 4,6 5 7 test functions are controlled via tm0-1 pins continuous signal light zero bit stream normal operation 10-11 tm0-1 r 0 level at tm0-1 12 rdist r 0 1 receive data normal receive data over distortion limit 13 fibbr r 0 1 filler signal or data is received no edges on receive data 14-15 lmode0-1 r/w 0 1 2 3 l_errn active by fibbr and rdist l_errn active by rdist l_errn active by fibbr l_errn is inactive 3h 0 intfl0 r 0 1 interrupt int0 not active interrupt int0 active 1 enint0 r/w 0 1 interrupt int0 disabled interrupt int0 disabled 2 polint0 r/w 0 1 interrupt int0 1-active interrupt int0 0-active 3 intfl1 r 0 1 interrupt int1 not active interrupt int1 active 4 enint1 r/w 0 1 interrupt int1 disabled interrupt int1 enabled 5 polint1 r/w 0 1 interrupt int1 1-active interrupt int1 0-active 6 comact r 0 1 no transmission block is processed transmission block is processed 7 comblk r 0 1 transmission block 0 is processed transmission block 1 is processed 8 entmt r/w 0 1 do not send data telegrams send data telegrams 9 fltmt r 0 1 data telegram is not sen t data telegram is sent 10 flrwait r 0 1 data telegram is not expected data telegram is expected 11 flrec r 0 1 data telegram is not received data telegram is received ? sercon410b 18/30
control register addresses (continued) a6-1 bit name r/w value function 3h 12 dmareqt r 0 1 dma request of transmit fifo inactive dma request of transmit fifo active 13 dmareqr r 0 1 dma request of receive fifo inactive dma request of receive fifo active 14 idle r level at idle pin 15 recactn r level at recactn pin 4h int_n r 0 1 interrupt event has not occurred interrupt flag active, interrupt event has occurred clr_int_n w 0 1 do not modify interrupt flag clear interrupt flag 0 int_rdist r/w interrupt receive data distorted 1 int_fibbr r/w interrupt no receive data 2 int_comblk0 r/w interrupt start transmission block 0 3 int_comblk1 r/w interrupt start transmission block 1 4 int_comend r/w interrupt end of transmission block 5 int_phas0 r/w interrupt phase mst = 0. 6 int_phaserr r/w interrupt phase mst errored 7 int_mstearly r/w interrupt communication cycle start too early 8 int_mstlate r/w interrupt communication cycle start too late 9 int_mstmiss r/w interrupt mst missing twice 10 int_tstart r/w interrupt start of transmit telegram 11 int_tend r/w interrupt end of transmit telegram 12 int_rwait r/w interrupt start waiting for receive telegram 13 int_rstart r/w interrupt start of receive telegram 14 int_rend r/w interrupt end of receive telegram 15 int_rerr r/w interrupt error of receive telegram 5h 0-7 int_sc_0-7 r/w interrupt service container 8 int_rmiss r/w interrupt receive telegram missing twice 9-12 int_time0-3 r/w interrupt time tint0-3 13 int_divclk r/w interrupt divclk signal 14 int_progerr r/w interrupt programming error 15 int_newadr r/w interrupt address change ? sercon410b 19/30
control register addresses (continued) a6-1 bit name r/w value function 6h 0-15 en0_int_n r/w 0 1 interrupt flag does not activate int0 interrupt flag activates int0 bit assignment same as for address 4h 7h 0-15 en0_int_n r/w 0 1 interrupt flag does not activate int0 interrupt flag activates int0 bit assignment same as for address 5h 8h 0-15 en1_int_n r/w 0 1 interrupt flag does not activate int1 interrupt flag activates int1 bit assignment same as for address 4h 9h 0-15 en1_int_n r/w 0 1 interrupt flag does not activate int1 interrupt flag activates int1 bit assignment same as for address 5h oah 0-7 phas0 r/w phase for mst transmit (master) or mst receive (slave) (reset value = 0ffh) 8-15 phas1 r/w phase for mst receive (slave) (reset value = 0ffh) obh 0-7 phasrec r phase information of received mst 8-15 recadr r address of receive telegram 0ch 0 msten r/w 0 1 mst is not transmitted or received mst is transmitted or received (sercos interface mode) 1 mstmaster r/w 0 1 receive mst (sercos interface slave) transmit and receive mst (sercos interface master) 2 comblk0 r/w 0 1 when phase = phas0 transmission block 0 is processed when phase = phas0 transmission block 1 is processed 3 comblk1 r/w 0 1 when phase = phas1 transmission block 0 is processed when phase = phas1 transmission block 1 is processed 4 con_clk r level at con_clk pin 5 enconclk r/w 0 1 con_clk pin doesn't become active con_clk pin becomes active from tint0 to tint1 6 polconclk r/w 0 1 signal at con_clk is 1-active signal at con_clk is 0-active 7 cyc_clk r level at cyc_clk pin 8 encycclk r/w 0 1 cyc_clk pin does not trigger timing control cyc_clk pin triggers timing control after tcycstart ? sercon410b 20/30
control register addresses (continued) a6-1 bit name r/w value functio n och 9 polcycclk r/w 0 1 timing control triggered by rising edge of cyc_clk timing control triggered by falling edge of cyc_clk 10 cycstart w 0 1 no function trigger timing control after tcycstart (master) 11 rdtcnt w 0 1 do not read tcnt load tcnt to tcntrd 12-15 ncyc r/w number of communcation cycles triggered by cyc_clk or cycstart 0dh 0-7 hs_timeout r/w handshake timeout for service channel 8-15 busy_timeout r/w busy timeout for service channel 0eh 0-4 mclkdiv r/w predivider value: fmclk/1 mhz - 1 (reset value = 19) 5-7 (not used) 8-12 mclkst r/w initial value for predivider 13-15 (not used) 0fh 0-15 tscyc0 r/w sercos interface cycle time in ? s for transmission block 0 10h 0-15 tscyc1 r/w sercos interface cycle time in ? s fr transmission block 1 11h 0-15 tcycdel r time at which mst is received, ring delay (master) 12h 0-15 tcntlt r stored value of tcnt time counter 13h 0-15 tcntst r/w initial value for tcnt time counter 14h 0-15 tcycstart r/w delay in triggering timing control 15h 0-15 jtscyc1 r/w receive time window for mst 1 16h 0-15 jtscyc2 r/w receive time window for mst 2 17h 0-15 progerr_fl r error flags clr_progerr_fl w clear error flags 18h 0-15 jtrdel1 r/w receive time window for data telegram 1 19h 0-15 jtrdel2 r/w receive time window for data telegram 2 1ah 0-15 tint0 r/w time at which time interrupt 0 and first edge of con_clk occur 1bh 0-15 tint1 r/w time at which time interrupt 1 and second edge of con_clk occur ? sercon410b 21/30
control register addresses (continued) a6-1 bit name r/w value function 1ch 0-15 tint2 r/w time at which time interrupt 2 occurs 1dh 0-15 tint3 r/w time at which time interrupt 3 occurs 1eh 0-15 tdivclk r/w time at which the first pulse of div_clk occurs 1fh 0-15 dtdivclk r/w div_clk pulse distance 20h 0-7 ndivclk r/w number of div_clk pulses within one communication cycle (reset value =0) 8 poldivclk r/w 0 1 pulses from div_clk are 1-active pulses from div_clk are 0-active 9-15 (not used) 21h 0-9 thtpt r internal ram address of telegram header of transmitted telegram 10-15 (not used) 22h 0-15 tht r control word 0 of telegram header of transmitted telegram 23h 0-9 thwpt r internal ram address of telegram header of a telegram which is expected 10-15 (not used) 24h 0-15 thw r control word 0 of telegram header of telegram which is expected 25h 0-9 thrpt r internal ram address of telegram header of received telegram 10 msttchk r/w 0 1 mst receive time is not checked mst receive time is checked 11 phas12 r/w 0 1 normal operation operating mode for sercos interface phase 1 and 2 12 flmdtadr r/w 0 1 address of receive telegram different from expected value address of receive telegram equal to expected value 13-15 (not used) 26h 0-15 thr r control word 0 of telegram header of received telegram 27h 0-15 rfifo r receive fifo 0-15 tfifo w transmit fifo ? sercon410b 22/30
4.2 data structures within the ram in this ram the first eleven words have a fixed meaning. a10-1 contents 0-1 compt0-1: start of transmission blocks 0-1 2-9 scpt0-7: address service containers 0-7 10 nmsterr: error counter mst 4.2.1 telegram headers a telegram header for receive telegram contains thefollowing five control words: index bit name function 0 0-7 adr telegram address 8 dma data storage in the internal ram (dma = 0) or dma transfer (dma = 1) 9 dbuf data in the ram: single buffer (dbuf = 0) or double buffer (dbuf =1) 10 val for single buffering (dma = 0, dbuf = 0) or dma transfer (dma = 1): telegram data is invalid (val = 0) or valid (val = 1); for double buffering (dma = 0, dbuf = 1): data in buffer 0 (val = 0) or buffer 1 (val = 1) is valid. modified by controller at beginning and end of receive telegrams. 11 achk telegrams are received if the address is valid (achk = 1) or independent on the received address (achk = 0). the received address is stored at adr. 12 tchk the time of receiving is checked (tchk = 1) or not checked (tchk = 0). 13 rerr the last telegram was free of error (rerr = 0) or errored or not received (rerr = 1). 14 0 marker bit for telegram header of receive telegram. 15 0 marker bit for telegram header. 1 0-15 trt time for the start of telegram in m s after end of mst. 2 0-15 tlen length of telegram in data words (not including address). 3 0-9 pt word address within the ram of the next telegram header or the end marker. 10-15 (not used) 4 0-15 nerr error counter the rest of the ram can be divided into data structures as required. ? sercon410b 23/30
a telegram header for transmit telegram comprises four control words: data structures within the ram (continued) index bit name function 0 0-7 adr telegram address 8 dma data storage in the ram (dma = 0) or dma transfer (dma = 1). 9 dbuf data in ram: single buffer (dbuf = 0) or double buffer (dbuf = 1). 10 val for double buffering (dma = 0, dbuf = 1): data in buffer 0 (val = 0) or buffer 1 (val = 1) are valid. set by processor. 11-12 en data telegram is not to be transmitted (en = 0), transmitted once (en = 1), continuously (en = 2) or transmitted only if the previously received telegram contains the expected address (en = 3) (phas12 =1 and flmdtadr = 1). if en is 1 the circuit sets en to 0 after the transmit telegram has been started. 13 (not used) 14 1 marker bit for telegram header of transmit telegram. 15 0 marker bit for telegram header. 1 0-15 trt time for the start of telegram in ? s after the end of mst. 2 0-15 tlen length of the telegram in data words (not including address). 3 0-9 pt word address of the next telegram header or the end marker. 10-15 (not used) ? sercon410b 24/30
data structures within the ram (continued) 4.2.2 data containers a data container comprises one or two 16-bit con- trol words as well as a variable number of data words. if the data is stored in the internal ram (dma = 0) and a single buffer is used (dbuf = 0), the data container has one buffer. using ram index bit name function 0 0-9 len number of 16-bit data words of the data block. 10 svfl flag, whether data block uses service container (svfl = 1). 11-13 nsv number of service container, which is used (0 - 7). 14 scmaster processing of service container in slave mode (scmaster = 0) or master mode (scmaster = 1). 15 lastdc last data container of the telegram (1) or further data containers follow (0). 1 0-15 pos position of the data block within the telegram in number of words. the first data record of a telegram has pos = 0 (only in case of receive telegrams). figure 13. structure of data containers storage and double buffering (dbuf = 1), two data buffers are needed. in case of dma transfer (dma = 1) the data container only comprises the control words (fig. 13). the structure of the two control words depends on whether a telegram is transmit- ted or received: ? sercon410b 25/30
data structures within the ram (continued) 4.2.3 end marker the end marker comprises two 16-bit words: index bit name function 0 0-13 (not used) 14 1 marker bit for the end marker. 15 1 marker bit for the end marker. 1 0-15 tend time after end of mst at which the last telegram has ended (in m s). figure 14. structure of service container 4.2.4 service containers a service container contains 5 control words and a buffer (buflen words, max. length 255) (fig. 14) ? sercon410b 26/30
data structures within the ram (continued) index bit name function 0 0 hs_mdt handshake-bit in mdt 1 l/s_mdt read/write in mdt 2 end_mdt end in mdt 3-5 elem_mdt data element type in mdt 6 setend end_mdt is to be set 7 m_busy service container waits for interaction of microprocessor (m_busy = 1) 8-9 ninfo_write number of info words in write buffer (1 to 4) 10-11 (not used) 12 int_err slave reports error 13 int_end_wrbuf end of write buffer is reached 14 int_end_rdbuf end of read buffer is reached 15 (not used) 1 0 hs_at handshake bit in at 1 busy_at busy bit in at 2 err_at error bit in at 3 cmd_at command modification bit in at 4-6 (not used) 7 recerr last transmission was correct (0) or errorneous (1) 8-9 ninfo_read number of info words in read buffer (1 to 4) 10-15 (not used) 2 0-7 wrdatpt pointer to present position in write buffer 8-15 wrdatlast pointer to last position in write buffer 3 0-7 rddatpt pointer to present position in read buffer 8-15 rddatlast pointer to last position in read buffer 4 0-7 err_cnt error counter 8 busy_cnt error counts differences of handshake (0) or busy cycles (1) 9 int_sc_err interrupt due to protocol error 10 int_hs_timeout interrupt due to handshake timeout 11 int_busy_timeout interrupt busy timeout 12 int_cmd slave has set command modification bit 13-15 (not used) for master mode (scmaster = 1) the control words are coded as follows: ? sercon410b 27/30
data structures within the ram (continued) the coding of the five control words depends on the mode of the service channel. using the slave mode (scmaster = 0) they have the following structure: index bit name function 0 0 hs_at handshake bit in at 1 busy_at busy bit in at, also waiting for microprocessor interaction 2 err_at error bit in at 3 error bit in at command modification bit in at 4-6 elem data element of present transmission 7 l/s read (0)/write (1) of present transmission 8-9 ninfo_write number of info words in write buffer (1 to 4) 10-11 (not used) 12 int_elem_change master has modified data element or read/write 13 int_end_wrbuf end of write buffer is reached 14 int_end_rdbuf end of read buffer is reached 15 int_end_mdt master reports end via end_mdt-bit 1 0 hs_mdt handshake bit in mdt 1 l/s_mdt read/write in mdt 2 end_mdt end bit in mdt 3-5 elem_mdt data element in mdt 6 (not used) 7 recerr last transmission was correct (0) or errorneous (1) 8-9 ninfo_read number of info words in read buffer (1 to 4) 10-15 (not used) 2 0-7 wrdatpt pointer to present position in write buffer 8-15 wrdatlast pointer to last position in write buffer 3 0-7 rddatpt pointer to present position in read buffer 8-15 rddatlast pointer to last position in read buffer 4 0-8 (not used) 9 int_sc_err interrupt due to protocol error 10-15 (not used) ? sercon410b 28/30
5 package mechanical data figure 15. sercon410b 100 pin plastic quad flat pack package dim. mm inches min typ max min typ max a 3.40 0.134 a2 2.55 2.80 3.05 0.100 0.110 0.120 d 23.65 23.90 24.15 0.931 0.941 0.951 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.85 0.742 e 17.65 17.90 18.15 0.695 0.705 0.715 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.35 0.486 e 0.65 0.026 number of pins nd 30 ne 20 n 100 6 additional support and tools 6.1 sercos interface specification the sercos interface specification is available at: f?rdergemeinschaft sercos interface e.v. herseler str. 31 d-50389 wesseling tel. xx49-2236-1517 fax. xx49-2236-1542 6.2 software and boards for the sercon410b driver software sercdrv master and slave routines for the sercon410b written in ansi-c independent from operating system and processor contains: - initialization - start-up of sercos interface (phases 0 - 4) - service channel transmission easy portable to many microprocessors and hard- ware platforms pc-at board serceb 16-bit isa bus receiver and transmitter for fibre optics (sercos interface standard) sercon410b and additional timerchip 82c54 additional rs-485-signals for serial connection and synchronization wire wrap area for extension add-on board sercint multiplexed 16-bit address/data-bus receiver and transmitter for fibre optics (sercos interface standard) sercon410b additional rs-485-signals for serial connection these software and boards are available at: iam gmbh vertrieb systemtechnik richard-wagner-str. 1 d-38106 braunschweig tel. xx49-531-3802-0 fax. xx49-531-3802-110 ? sercon410b 29/30
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. notes: ? sercon410b 30/30

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